Record number :
1366881
Title of article :
High Speed Delay-Locked Loop for Multiple Clock Phase Generation
Author/Authors :
قنبري، اشكان نويسنده 1Graduate School of Electrical Engineering, Qazvin Islamic Azad University (QIAU), Qazvin, Iran Ghanbari, A , صدر، علي نويسنده , , نيكو، مهران نويسنده ,
Issue Information :
فصلنامه با شماره پیاپی 0 سال 2013
Pages :
9
From page :
19
To page :
27
Abstract :
In this paper, a high speed delay-locked loop (DLL) architecture is presented which can be employed in high frequency applications. In order to design the new architecture, a new mixed structure is presented for phase detector (PD) and charge pump (CP) which can be triggered by double edges of the input signals. In addition, the blind zone is removed due to the elimination of reset signal. Therefore, operating frequency of the whole system is improved which can be mentioned as notable advantage of the proposed DLL. To obtain more accurate phases at the output signal, a new delay cell is introduced which is controlled by a single voltage. This control voltage, through equalizing the rise and fall time, regulate duty cycle of output clock. These features along with simplicity and low power consumption qualify the proposed architecture to be widely used in high speed systems. For better realization of the designed circuit’s behavior, simulation results are presented based on TSMC 0.35?m CMOS technology and 3.3-V power supply for a type II filter which demonstrate accuracy and perfect performance of this work.
Journal title :
Journal of Electrical and Computer Engineering Innovations (JECEI)
Link To Document :