Record number :
100095
Title of article :
A DDS-based PLL for 2.4-GHz frequency synthesis
Author/Authors :
A.، Bonfanti, نويسنده , , F.، Amorosa, نويسنده , , C.، Samori, نويسنده , , A.L.، Lacaita, نويسنده ,
Issue Information :
روزنامه با شماره پیاپی سال 2003
Pages :
-1006
From page :
1007
To page :
0
Abstract :
In this transactions brief, we present a direct digital synthesizer (DDS)-based phase-locked loop (PLL), for frequency synthesis at 2.4 GHz with 80-MHz tuning range. The DDS signal is mixed with the voltage-control oscillator output in the PLL feedback path. This solution helps in avoiding some of the typical tradeoffs in PLL. In particular, it is possible to achieve a very high-frequency resolution together with fast settling and spectral purity. These characteristics are often incompatible both in integer and fractional dividers PLL. A prototype was fabricated on PCBs and tested. The settling time is about 3 (mu)s for 0.1 ppm (240 Hz) accuracy. Worst-case spurs are -53 dBc at 8-MHz offset from the carrier. The integrated phase noise in the band 1 kHz -1 MHz is 0.9(degree) rms. This architecture is also suitable for direct frequency modulation, without necessitating any calibration system.
Keywords :
Abdominal obesity , Food patterns , Prospective study , waist circumference
Journal title :
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II:ANALOG AND DIGITAL SIGNAL PROCESSING
Journal title :
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II:ANALOG AND DIGITAL SIGNAL PROCESSING
Serial Year :
2003
Link To Document :
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