Record number :
100082
Title of article :
A dual-slope phase frequency detector and charge pump architecture to achieve fast locking of phase-locked loop
Author/Authors :
Cheng، Kuo-Hsing نويسنده , , Yang، Wei-Bin نويسنده , , Ying، Cheng-Ming نويسنده ,
Issue Information :
روزنامه با شماره پیاپی سال 2003
Pages :
-891
From page :
892
To page :
0
Abstract :
In this paper, a dual-slope phase frequency detector and charge pump architecture to achieve fast locking of phase-locked loops is proposed and analyzed. The proposed topology is based on two tuning loops: a fine-tuning loop and a coarse-tuning loop. A coarse-tuning loop is used for fast convergence, and a fine-tuning loop is used to complete fine adjustments. The proposed phased-locked loop (PLL) circuit is designed based on the TSMC 0.35-(mu)m 1P4M CMOS process with a 3.3-V supply voltage. HSPICE simulation shows that the lock time of the proposed PLL can be reduced over 82% in comparison to the conventional PLL. An experimental chip was implemented and measured. The measurement results show that the proposed PLL has fast locking properties.
Keywords :
Abdominal obesity , Food patterns , Prospective study , waist circumference
Journal title :
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II:ANALOG AND DIGITAL SIGNAL PROCESSING
Journal title :
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II:ANALOG AND DIGITAL SIGNAL PROCESSING
Serial Year :
2003
Link To Document :
بازگشت