Record number :
100000
Title of article :
Area-optimized implementation of quadrature direct digital frequency synthesizers on LUT-based FPGAs
Author/Authors :
F.، Cardells-Tormo, نويسنده , , J.، Valls-Coquillat, نويسنده ,
Issue Information :
روزنامه با شماره پیاپی سال 2003
Pages :
-134
From page :
135
To page :
0
Abstract :
This paper deals with an field-programmable gate array (FPGA)-implementation of quadrature direct digital frequency synthesizers (QDDFS), and, in particular, with those based on CORDIC, interpolation, and memory compression. We provide results of maximum throughput, i.e., 302 MHz, when mapping QDDFS architectures on current look-up-table (LUT)-based field-programmable technology. We take into account those VLSI design guidelines that work well on FPGAs and architectural considerations to design efficient (in terms of area and throughput) QDDFS, up to 56% faster than commercial cores. Finally, we present a design map that combines the phase-toamplitude techniques reviewed in this paper so as to minimize the overall area.
Keywords :
natural convection , Analytical and numerical techniques , heat transfer
Journal title :
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II:ANALOG AND DIGITAL SIGNAL PROCESSING
Journal title :
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II:ANALOG AND DIGITAL SIGNAL PROCESSING
Serial Year :
2003
Link To Document :
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